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mehrere oft verwendete Routinen in eigene utils.py eingebaut

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This commit is contained in:
Michael Stangl
2026-01-23 10:23:18 +01:00
parent 37208f61b1
commit 3deebb81f3
9 changed files with 453 additions and 175 deletions
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.vscode/launch.json
Vendored
+34 -6
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@@ -123,35 +123,35 @@
]
},
{
"name": "getpositions with ST500592_Omniflo.dxf",
"name": "getpositions with PR500592_10_5.13_POT_20251216.dxf",
"type": "debugpy",
"request": "launch",
"program": "${file}",
"console": "integratedTerminal",
"args": [
"--filename",
"ST500592_Omniflo.dxf",
"PR500592_10_5.13_POT_20251216.dxf",
"--sensors",
"--rack",
"--console",
"--write",
"ST500592_Omniflo_positions.json"
"PR500592_10_5.13_POT_20251216_positions.json"
]
},
{
"name": "getpositions with ST500592_10_5-11_ILS.dxf",
"name": "getpositions with POT_ST1_ST6_12.dxf",
"type": "debugpy",
"request": "launch",
"program": "${file}",
"console": "integratedTerminal",
"args": [
"--filename",
"ST500592_10_5-11_ILS.dxf",
"POT_ST1_ST6_12.dxf",
"--sensors",
"--rack",
"--console",
"--write",
"ST500592_10_5-11_ILS_positions.json"
"POT_ST1_ST6_12_positions.json"
]
},
{
@@ -289,6 +289,21 @@
"ST-Fortna_ASCII_cables.dxf"
]
},
{
"name": "draw cables for test.json",
"type": "debugpy",
"request": "launch",
"program": "${file}",
"console": "integratedTerminal",
"args": [
"--filename",
"test_todraw.json",
"-n",
"test_cables.dxf",
"-x",
"test_cables.xlsx"
]
},
{
"name": "routing for easy_positions.json",
"type": "debugpy",
@@ -316,6 +331,19 @@
"-g"
]
},
{
"name": "routing for test_positionsdraw.json",
"type": "debugpy",
"request": "launch",
"program": "${file}",
"console": "integratedTerminal",
"args": [
"--filename",
"test_positionsdraw.json",
"-w",
"test_draw.json",
]
},
{
"name": "run_tests.py with easy_3tunnels.dxf",
"type": "debugpy",